Multiple-processor error detection system and method thereof
AssigneeHyundai Autron Co., Ltd.
InventorsKee Beom KIM, Young Suk Kim
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Abstract
Provided is an error detection system including: an input unit for setting a system operation request time based on an external input; a plurality of processors for performing a predetermined operation; and an error detection processor for detecting an error of each of the plurality of processors. The error detection processor transmits an error detection signal to a predetermined first processor of the plurality of processors, receives an updated error detection signal from a predetermined second processor among the plurality of processors, and determines whether the operation processing time of the plurality of processors is processed within the operation request time based on the updated error detection signal.
Claims20
An error detection system comprising:
- an input unit for setting a system operation request time based on an external input;
- a plurality of processors for performing a predetermined operation;
- and
- an error detection processor for detecting an error of each of the plurality of processors,
- wherein the error detection processor transmits an error detection signal to a predetermined first processor of the plurality of processors,
- receives an updated error detection signal from a predetermined second processor among the plurality of processors, and
- determines whether the operation processing time of the plurality of processors is processed within the operation request time based on the updated error detection signal.
An error detection method comprising:
- setting a system operation request time based on an external input;
- transmitting an error detection signal to a predetermined first processor by an error detection processor,
- performing a predetermined operation by each of the plurality of processors;
- updating an error detection signal by each of the plurality of processors;
- receiving an updated error detection signal from a predetermined second processor among the plurality of processors by an error detection processor;
- and
- determining whether the operation processing time of the plurality of processors is processed within the operation request time based on the updated error detection signal by an error detection processor.
Dependencies are inferred from the claim text.