Method and apparatus for guest return address stack emulation supporting speculation

A microprocessor comprising:

• an out-of-order microprocessor pipeline, wherein said pipeline is configured to perform operations comprising:
• mapping a plurality of instructions in a guest address space to a corresponding plurality of instructions in a native address space and
• for each of one or more function calls made in said native address space, performing:
• pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein said GRAS is maintained at a fetch stage of said pipeline, and wherein said current entry includes a guest target return address and a corresponding native target return address associated with said function call,
• popping said current entry from said GRAS in response to processing a return instruction,
• comparing contents of said current entry with contents of an entry popped from a return address stack (RAS) maintained at a later stage of said pipeline with respect to said fetch stage of said pipeline, wherein said native target return address in said current entry is attached to said return instruction and sent through said pipeline along with said return instruction to said later stage of said pipeline, and
• responsive to a determination based on said comparing that said native target return address in said current entry does not match a return address in said entry popped from said RAS, fetching instructions from said return address in said entry popped from said RAS.

An apparatus to speculatively maintain a guest return address stack (GRAS) of an out-of-order microprocessor pipeline, said apparatus comprising:

• a memory;
• and
• a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and wherein said processor is configured to perform operations comprising:
• mapping a plurality of instructions in a guest address space to a corresponding plurality of instructions in a native address space and
• for each of one or more function calls made in said native address space, performing:
• pushing a current entry into a GRAS responsive to a function call, wherein said GRAS is maintained at a fetch stage of said pipeline, and wherein said current entry includes a guest target return address and a corresponding native target return address associated with said function call,
• popping said current entry from said GRAS in response to processing a return instruction,
• comparing contents of said current entry with contents of an entry popped from a return address stack (RAS) maintained at a later stage of said pipeline with respect to said fetch stage of said pipeline, wherein said native target return address in said current entry is attached to said return instruction and sent through said pipeline along with said return instruction to said later stage of said pipeline, and
• responsive to a determination based on said comparing that said native target return address in said current entry does not match a return address in said entry popped from said RAS, fetching instructions from said return address in said entry popped from said RAS.