System and method for multiplexing vector compare

A machine-readable medium having instructions stored therein which, when executed, cause a processor to perform a set of operations, the set of operations comprising:

• loading a first vector having a vector length, wherein the first vector includes a plurality of vector portions of a vector portion length;
• loading a second vector having the vector length, wherein the second vector includes a same quantity of vector portions as the plurality of vector portions, and wherein the vector portions of the second vector are of the vector portion length;
• performing a comparison of each of the plurality of vector portions of the first vector to each bit of each of the plurality of vector portions of the second vector;
• and
• storing a result of the performing in a third vector with at least one bit of the third vector corresponds to each of the bit-wise logical AND of vector portions.

A computing device comprising:

• a memory to store data and instructions;
• an interconnect to communicatively couple the memory and a processor;
• and
• the processor configured to include first circuitry to access a first vector having a vector length, wherein the first vector comprises a plurality of vector portions having a vector portion length, second circuitry to access a second vector of the vector length, wherein the second vector comprises a same quantity of vector portions as the plurality of vector portions, and wherein the vector portions of the second vector are of the vector portion length, third circuitry to perform a comparison of each of the plurality of vector portions of the first vector to each of the plurality of vector portions of the second vector, and fourth circuitry to store a result of the comparisons in a third vector with at least one bit of the third vector corresponding to each of the comparison of the pluralities of the first and the second vector portions, wherein the first, second, third and fourth circuitry are to perform all of their functions responsive to execution of one machine language instruction by the processor.