Compiler for a Processor Comprising Primary and Non-Primary Functional Units
AssigneeInternational Business Machines Corporation
InventorTyler J. Kenney
Life of this patent
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Abstract
A computer-implemented method for generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit is provided. Source code is translated into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model. The representative primary functional unit instructions are transformed into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.
Claims7
A computer-implemented method of generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit, comprising:
- translating source code into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model, wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model;
- and
- transforming the representative primary functional unit instructions into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.
Dependencies are inferred from the claim text.