Metastable true random number generator realized on fpga

A metastable true random number generator realized on an FPGA, characterized in that comprises:

• a 1st decoder;
• a 2nd decoder;
• a binary counter;
• a D flip-flop;
• a delay circuit;
• and
• a postprocessing circuit,
• wherein the binary counter is used for outputting a 12-bit digital signal,
• wherein the 1st decoder and the 2nd decoder are each provided with a 6-bit input terminal and a 32-bit output terminal,
• wherein a higher 6-bit digital signal of the 12-bit digital signal output by the binary counter is accessed to the 6-bit input terminal of the 1st decoder, and a lower 6-bit digital signal of the 12-bit digital signal output by the binary counter is accessed to the 6-bit input terminal of the 2nd decoder,
• wherein the D flip-flop is provided with an input terminal, a clock terminal and an output terminal,
• wherein the delay circuit comprises a configurable delay chain, wherein the configurable delay chain comprises a rough adjustment circuit and a fine adjustment circuit,
• wherein the rough adjustment circuit comprises 32 rough adjustment cells, each rough adjustment cell is provided with an input terminal, a configuration terminal and an output terminal. wherein the input terminal of the 1st rough adjustment cell is the input terminal of the rough adjustment circuit, wherein the output terminal of the nth rough adjustment cell is connected to the input terminal of the (n+1)th rough adjustment cell, wherein n=1, 2, . . . , 31, and the output terminal of the 32nd rough adjustment cell is the output terminal of the rough adjustment circuit, wherein the configuration terminals of the 32 rough adjustment cells form the 32-bit configuration terminal of the rough adjustment circuit,
• wherein each rough adjustment cell comprises a 1st 6-input lookup table and a two-to-one selector,
• wherein each 1st 6-input lookup table is provided with 6 input ports and an output port. Each two-to-one selector is provided with a 1st input terminal, a 2nd input terminal, a selection terminal and an output terminal,
• wherein the 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell, and the 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0,
• wherein the output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector,
• wherein the selection terminal of each two-two-one selector is the configuration terminal of the corresponding rough adjustment cell, and the output terminal of each two-to-one selector is the output terminal of the corresponding rough adjustment cell.
• wherein the fine adjustment circuit is provided with an input terminal, a 32-bit configuration terminal and an output terminal,
• wherein the input terminal of the rough adjustment circuit is connected to the clock terminal of the D flip-flop,
• wherein the 32-bit configuration terminal of the rough adjustment circuit is connected to the 32-bit output terminal of the 1st decoder in a one-to-one corresponding mode, and the output terminals of the rough adjustment cells are connected to the input terminal of the fine adjustment circuit, wherein the output terminal of the fine adjustment circuit is connected to the input terminal of the D flip-flop,
• wherein the 32-bit configuration terminal of the fine adjustment circuit is connected to the 32-bit output terminal of the 2nd decoder in a one-to-one corresponding mode,
• wherein the metastable true random number generator further comprises a sampling analysis circuit and a monitoring circuit,
• wherein the output terminal of the D flip-flop is connected to the input terminal of the postprocessing circuit and the input terminal of the sampling analysis circuit, wherein the output terminal of the sampling analysis circuit is connected to the input terminal of the monitoring circuit, wherein the output terminal of the monitoring circuit is connected to the input terminal of the binary counter,
• wherein the sampling analysis circuit acquires output data of the output terminal of the D flip-flop in real time, every 200 bits of output data acquired are regarded as a set, and the percent of 1 in this set of output data is calculated;
• and the calculation result is then sent to the monitoring circuit, and the monitoring circuit generates a control signal according to the calculation result and sends the control signal to the binary counter,
• when the percent of 1 is over 80%, the monitoring circuit controls the value of the binary counter to plus 3,
• when the percent of 1 is smaller than 80% and greater than 52%, the monitoring circuit controls the value of the binary counter to plus 1,
• when the percent of 1 is smaller than 52% and greater than 48%, the monitoring circuit keeps the value of the binary counter unchanged,
• when the percent of 1 is smaller than 48% and greater than 20%, the monitoring circuit controls the value of the binary counter to minus 1,
• when the percent of 1 is smaller than 20%, the monitoring control module controls the value of the binary counter to minus 3,
• wherein under the control of the monitoring circuit, the binary counter generates and outputs a corresponding 12-bit digital signal,
• wherein under the control of the binary counter, the 1st decoder and the 2nd decoder generate corresponding decoding signals to configure the rough adjustment circuit and the fine adjustment circuit in real time.