Back to results
US 2019/0155370 A1Published application
Selecting A Low Power State Based On Cache Flush Latency Determination
AssigneeIntel Corporation
InventorsSundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
Life of this patent
Estimating the term…
Abstract
In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a plurality of cores to independently execute instructions;
- a cache memory associated with at least one of the plurality of cores, the cache memory including a plurality of lines to store data;
- and
- one or more counters to maintain count information associated with the cache memory;
- and
- a power controller including a low power controller to determine a low power state for the processor to enter based on a comparison of a break even residency time for a first low power state to an expected idle time duration, the break even residency time based at least in part on the count information associated with the cache memory, enable the processor to enter into the first low power state if the break even residency time is greater than the expected idle time duration time and prevent the processor from entry into the first low power state if the break even residency time is less than the expected idle time duration.
3 more elements
A mobile phone comprising:
- a processor comprising:
- a plurality of cores each having at least one cache memory;
- a counter storage to maintain count information for the at least one cache memory;
- and
- a power controller to determine a break even residency value for a target low power state based at least in part on the count information and compare the break even residency value to a time duration until a next expected event, and cause the processor to enter into the target low power state based on a first result of the comparison of the break even residency value to the time duration;
- and
- a flash memory coupled to the processor.
4 more elements
A method comprising:
- maintaining count information of a cache memory of a processor;
- determining a flush latency for flushing the cache memory based at least in part on the count information;
- determining a break even value based at least in part on the flush latency;
- responsive to a low power state request, selecting, from a plurality of low power states, a low power state for the processor to enter based at least in part on a comparison of the break even value to an expected idle duration;
- and
- causing the processor to enter a low power state of the low power state request based on the comparison of the break even value to the expected idle duration, and otherwise determining whether another low power state is available for the processor.
3 more elements
Dependencies are inferred from the claim text.