Multi-level loops for computer processor control

A non-transitory machine-readable medium having stored thereon instructions, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform:

• concurrently executing an outer control loop and an inner control loop, the outer control loop to monitor an operating characteristic of a System on a Chip (SoC), and the inner control loop to monitor an operating characteristic of a first processing domain included in the SoC, the SoC comprising a plurality of processing domains, each processing domain comprising one or more processing cores;
• determining, based on the operating characteristic of the SoC monitored by the outer control loop, a first control action for the first processing domain;
• determining, based on the operating characteristic of the first processing domain monitored by the inner control loop, a control action for the first processing domain;
• based on a comparison of the first control action and the second control action, selecting one of the first control action and the second control action as a selected control action, wherein the first control action is not applied prior to the comparison, wherein the second control action is not applied prior to the comparison;
• and
• applying the selected control action to the first processing domain.