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US 2019/0155174 A1Published application
Semiconductor device having overlay pattern
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-sun KIM, Young-sik PARK, Min-keun KWAK, Byoung-hoon KIM, Yong-chul KIM, Hyun-jeong LEE, Sung-won CHOI
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Abstract
A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.
Claims20
A semiconductor device, comprising:
- a semiconductor substrate comprising an in-cell area and a scribe lane defining the in-cell area;
- a first overlay pattern on the semiconductor substrate;
- and
- a second overlay pattern adjacent to the first overlay pattern,
- wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern, and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.
2 more elements
A semiconductor device, comprising:
- a semiconductor substrate;
- a first overlay pattern on the semiconductor substrate, the first overlay pattern comprising line-and-space patterns each extending in a first direction and a second direction perpendicular to the first direction;
- and
- a second overlay pattern on the semiconductor substrate, the second overlay pattern surrounding the first overlay pattern within a forbidden region surrounding the first overlay pattern.
1 more element
A semiconductor device, comprising:
- a semiconductor substrate comprising an in-cell area and a scribe lane defining the in-cell area;
- a first overlay pattern on the semiconductor substrate;
- and
- a second overlay pattern adjacent to the first overlay pattern, the second overlay pattern being in a forbidden region of the first overlay pattern.
1 more element
Dependencies are inferred from the claim text.