Single lamination blind and method for forming the same
AssigneeR&D Circuits, Inc.
InventorsDonald Eric Thompson, Dhananjaya Turpuseema
Life of this patent
Estimating the term…
Abstract
A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.
Claims4
A method of forming a printed circuit board (PCB) while removing or preventing a stub from forming a via of a printed circuit board (PCS) the steps comprising:
- forming a multi-layered printed circuit board (PCB) of individual layers that are pressed together by first etching each of said individual layers of said PCB except for the an outer layer;
- placing a first signal trace on any one of said layers of said PCB;
- placing a second signal trace on another layer of said PCB;
- adding or inserting seed resist material to said layers of said PCB;
- drilling at least one via hole through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces;
- applying plating seed resist layer by electroless plating;
- and etching outer layers thereby preventing electrically conductive material from attaching to the walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via;
- adding or inserting a seed-resist material into said PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.
A structure for a multi-layered a printed circuit board (PCB) comprising:
- a multi-layered printed circuit board (PCB) formed of individual layers that pressed together that are first etching each of said individual layers of said PCB except for an outer layer;
- a first signal trace placed on any one of said layers of said PCB;
- a second signal trace placed on another layer of said PCB;
- adding or inserting seed resist material to said layers of said PCB;
- At least one via hole drilled through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces;
- plated seed resist layer applied by electroless plating to said layers;
- and said outer layers being etched thereby preventing electrically conductive material from attaching to walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via;
- seed-resist material added or inserted into said PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.
Dependencies are inferred from the claim text.