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US 2019/0115885 A1Published application
Biased amplifier
AssigneeTexas Instruments Incorporated
InventorSudheer PRASAD
Life of this patent
Estimating the term…
Abstract
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
Claims20
An amplifier, comprising:
- a bias circuit configured to generate a bias voltage with respect to ground;
- and
- an open-loop gain stage comprising:
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a gate terminal coupled to a first node, a source terminal coupled to a second node, a drain terminal coupled to a third node, and a bulk connection coupled to the bias circuit;
- a second PMOS having a gate terminal coupled to a ground node, a source terminal coupled to the second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the bias circuit;
- a first n-type MOSFET (NMOS) having a drain terminal and a gate terminal coupled to the third node and a source terminal coupled to a fifth node;
- a second NMOS having a drain terminal coupled to the fourth node, a gate terminal coupled to the third node;
- and a source terminal coupled to the fifth node, wherein the gain stage is configured to couple to an adjustable resistor positioned between the third node and the fourth node;
- and
- a buffer stage coupled to the open-loop gain stage at the fourth node and comprising a super source follower.
7 more elements
An amplifier, comprising:
- a bias circuit;
- and
- a buffer stage coupled to the bias circuit and comprising:
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a second node;
- a gate terminal coupled to a third node, a drain terminal coupled to a fourth node, and a bulk connection coupled to a first node, a first resistor coupleable between the first node and the second node;
- a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node, a gate terminal coupled to the bias circuit, and a source terminal configured to couple to a fifth node via a second resistor;
- and
- a second NMOS having a drain terminal coupled to the second node, a gate terminal coupled to the fourth node, and a source terminal coupled to the fifth node, wherein the buffer stage is configured to couple to a first capacitor and a third resistor coupled in series between the fourth node and the fifth node, and wherein the second node is an output of the amplifier.
5 more elements
An amplifier, comprising:
- a bias circuit;
- a compensation circuit;
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a first node, a gate terminal coupled to a second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the bias circuit;
- a second PMOS having a source terminal coupled to the first node, a gate terminal coupled to a third node, a drain terminal coupled to the compensation circuit at a fifth node, and a bulk connection coupled to the bias circuit;
- a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node and a gate terminal coupled to a sixth node;
- and
- a second NMOS having a drain terminal coupled to a source terminal of the first NMOS, a gate terminal coupled to the fourth node, and a source terminal coupled to a seventh node.
4 more elements
An amplifier, comprising:
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal configured to couple to a first node via a first resistor, a gate terminal coupled to a second node, and a drain terminal coupled to a third node;
- a second PMOS having a source terminal configured to couple to the first node via a second resistor, a gate terminal configured to couple to a fourth node via a first capacitor, and a drain terminal coupled to a fifth node;
- a first n-type MOSFET (NMOS) having a drain terminal coupled to the third node and a gate terminal coupled to a sixth node;
- a second NMOS having a drain terminal coupled to a source terminal of the first NMOS, a gate terminal coupled to the third node, and a source terminal coupled to a seventh node;
- a third NMOS having a gate terminal coupled to the sixth node, a drain terminal coupled to the fifth node, and a source terminal coupled to an eighth node;
- a fourth NMOS having a gate terminal coupled to the third node, a drain terminal coupled to the eighth node, and a source terminal coupled to the seventh node;
- and
- a fifth NMOS having a gate terminal coupled to the fifth node, a drain terminal coupled to a ninth node, and a source terminal coupled to the seventh node, wherein the amplifier is configured to couple to a second capacitor positioned between the eighth node and the ninth node, a third capacitor positioned between the ninth node and the second node, and a fourth capacitor positioned between the second node and the seventh node.
5 more elements
Dependencies are inferred from the claim text.