Inspection device

A checking apparatus for testing at least one first closed-loop control unit, wherein the checking apparatus comprises at least:

• a first computation unit for executing a model code, the model code being able to be used to provide a simulated controlled system signal for stimulating the closed-loop control unit and to manipulate an actuator signal of the closed-loop control unit, and a first time signal converter unit having at least
• (i) a first time signal interface for picking up a first time signal of a global time signal source, and (ii) a changeover signal transmission unit configured to provide a first changeover signal for forwarding to a first multiplexer, and (iii) a first timing transmission unit configured to generate a first periodic timing signal from the first time signal and to output the first periodic timing signal to a first PLL, and wherein the checking device furthermore comprises:
• (a) a first oscillator configured to generate a second periodic timing signal and to output the second periodic timing signal to a second PLL, and
• (b) a first clock, firstly connected to the first multiplexer by means of a timing signal line and secondly configured to forward a first clock signal to a first input/output unit and/or the first computation unit,
• wherein a first multiplexer input of the first multiplexer is connected to a first PLL output of the first PLL to transmit a first frequency-stabilized timing signal in the direction of the first multiplexer, and
• wherein a second multiplexer input of the first multiplexer is connected to a second PLL output of the second PLL to transmit a second frequency-stabilized timing signal in the direction of the first multiplexer, and
• wherein the first changeover signal is provided to be used to control the first multiplexer such that depending on a state of the changeover signal the first multiplexer can be used to forward either the first frequency-stabilized timing signal or the second frequency-stabilized timing signal to the first clock, and wherein the first clock is configured so as, depending on the state of the changeover signal, to process either the first frequency-stabilized timing signal or the second frequency-stabilized timing signal to generate the first clock signal.