Cloud scaling with non-blocking non-spinning cross-domain event synchronization and data communication

A method of simultaneously processing multiple virtual network functions (VNFs) by a processor, comprising:

• providing memory to store multiple virtual hardware thread (VHTR) descriptors, each comprising an architectural state, a monitored address range, a priority, and an execution state;
• fetching, by fetch circuitry, instructions associated with a plurality of the multiple VNFs;
• decoding, by decode circuitry, the fetched instructions;
• scheduling, by scheduling circuitry, the decoded instructions for execution by a plurality of cores, by:
• allocating and pinning a VHTR to each of the plurality of VNFs;
• scheduling execution of one of the pinned VHTRs by each of the plurality of cores;
• setting the execution state of each scheduled VHTR, using the priority of the VHTR, to one of E1, during which decoded instructions associated with the scheduled VHTR are executed, and E2, during which the VHTR is to wait to be promoted to E1;
• and
• in response to a monitor instruction received from a given VHTR, pausing and setting the execution state of the given VHTR to PAUSE, switching in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range of the given VHTR, triggering the given VHTR, and setting its execution state to TRIGGER.

A non-transitory computer-readable medium containing instructions that, when executed by a processor, cause the processor to simultaneously process multiple virtual network functions (VNFs) by a processor by:

• providing memory to store multiple virtual hardware thread (VHTR) descriptors, each comprising an architectural state, a monitored address range, a priority, and an execution state;
• fetching, by fetch circuitry, instructions associated with a plurality of the multiple VNFs;
• decoding, by decode circuitry, the fetched instructions;
• scheduling, by scheduling circuitry, the decoded instructions for execution by a plurality of cores, by:
• allocating and pinning a VHTR to each of the plurality of VNFs;
• scheduling execution of one of the pinned VHTRs by each of the plurality of cores;
• setting the execution state of each scheduled VHTR, using the priority of the VHTR, to one of E1, during which decoded instructions associated with the scheduled VHTR are executed, and E2, during which the VHTR is to wait to be promoted to E1;
• and
• in response to a monitor instruction received from a given VHTR, pausing and setting the execution state of the given VHTR to PAUSE, switching in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range of the given VHTR, triggering the given VHTR, and setting its execution state to TRIGGER.