System and techniques for encrypting chip-to-chip communication links
AssigneeIntel Corporation
InventorsSiddhartha Chhabra, Prashant Dewan
Life of this patent
Estimating the term…
Abstract
Embodiments detailed herein relate to techniques which enable the creation of secure point-to-point interconnect communication channels between hardware components which may be independently manufactured and arbitrarily paired with one another in a computer system. Also detailed herein is instruction support for dynamically enabling and disabling the security of a point-to-point interconnect link.
Claims25
An apparatus, comprising:
- a processing core;
- an input/output (I/O) port, coupled to the processing core, having circuitry to:
- establish a first secure communication channel between the processing core and a hardware component that is coupled to the I/O port via a point-to-point interconnect, wherein the first secure communication channel is established using a public key exchange protocol, and
- send a cryptographic key to the hardware component using the first secure communication channel, the cryptographic key used to establish a second secure communication channel between the processing core and a device coupled to the hardware component.
A processor comprising:
- decode circuitry to decode an instruction having an opcode, a first operand identifier, and a second operand identifier, wherein the identified first operand is to store a security request and the identified second operand is to store an ownership identifier;
- and
- execution circuitry to execute the decoded instruction to, responsive to determining that the security request indicates a request to establish a secure communication channel between a processing core and a hardware component that is coupled to an input/output (I/O) port via a point-to-point interconnect, cause first link security circuitry of the processing core and second link security circuitry of the hardware component to establish the secure communication channel using a public key exchange protocol.
A method comprising:
- decoding an instruction having an opcode, a first operand identifier, and a second operand identifier, wherein the identified first operand is to store a security request and the identified second operand is to store an ownership identifier;
- and
- executing the decoded instruction to, responsive to determining that the security request indicates a request to establish a secure communication channel between a processing core and a hardware component that is coupled to an input/output (I/O) port via a point-to-point interconnect, causes first link security circuitry of the processing core and second link security circuitry of the hardware component to establish the secure communication channel using a public key exchange protocol.
A non-transitory machine-readable medium storing an instruction which when executed by a processor causes the processor to perform a method, the method comprising:
- decoding an instruction having an opcode, a first operand identifier, and a second operand identifier, wherein the identified first operand is to store a security request and the identified second operand is to store an ownership identifier;
- and
- executing the decoded instruction to, responsive to determining that the security request indicates a request to establish a secure communication channel between a processing core and a hardware component that is coupled to an input/output (I/O) port via a point-to-point interconnect, causes first link security circuitry of the processing core and second link security circuitry of the hardware component to establish the secure communication channel using a public key exchange protocol.
Dependencies are inferred from the claim text.