Low ber hard-decision ldpc decoder
AssigneeToshiba Memory Corporation
InventorsPaul Edward Hanham, David Malcolm Symons, Neil Buxton
Life of this patent
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Abstract
A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.
Claims10
A method of Low Density Parity Check (“LDPC”) decoding by an LDPC decoder, the LDPC decoder operable to perform the steps comprising of:
- receiving a plurality of encoded data;
- and
- iteratively selecting a voting requirement, among a plurality of voting requirements, for LDPC decoding of each received encoded data of the plurality of encoded data,
- wherein for each iteration of the LDPC decoder,
- selecting is based on a value of a syndrome of the received encoded data;
- employing a bit-flipping scheme of the LDPC decoder according to the selected voting requirement, and
- correcting the encoded data based on the respective selected voting requirement and the employed bit-flipping scheme.
Dependencies are inferred from the claim text.