Clock circuit and method of operating the same

A method of operating a clock circuit, the method comprising:

• causing, by a first latch, a first latch output signal to transition from a first voltage level to a second voltage level in response to a transition of an enable signal from the second voltage level to the first voltage level, the second voltage level being different from the first voltage level;
• causing a clock trigger circuit to pull a first node from the first voltage level to the second voltage level in response to a transition of a first clock signal from the first voltage level to the second voltage level, the pulling of the first node thereby causing a first control signal of the clock trigger circuit to transition from the first voltage level to the second voltage level, the clock trigger circuit being coupled to at least an input of a first latch or a first trigger circuit by the first node, and the first control signal being fed back from the clock trigger circuit to the input of the first latch from the first node;
• and
• causing, by the first trigger circuit, an output clock signal to transition from the second voltage level to the first voltage level in response to the transition of the first clock signal to the second voltage level, and in response to the transition of the first latch output signal to the second voltage level.