Switched Resistance Device With Reduced Sensitivity to Parasitic Capacitance

A filter circuit comprising:

• a stacked switched resistance device comprising:
• an input configured to receive a signal to be filtered in the filter circuit;
• an output;
• and
• a plurality of segments connected in series between the input and the output and configured to produce a first effective resistance, each segment comprising:
• a resistor including an inherent resistance an inherent parasitic capacitance;
• and
• a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal;
• and
• wherein the first effective resistance of the stacked switched resistance device exceeds a second effective resistance of at least one resistor that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal, the at least one resistor having an inherent resistance that is equal to a sum of the inherent resistances of the resistors in the plurality of segments and an inherent parasitic capacitance that is equal to a sum of the inherent parasitic capacitances of the resistors in the plurality of segments;
• and
• a filter capacitor connected to the output of the stacked switched resistance device.