Circuit and architecture for a demodulator for a wireless power transfer system and method therefor

A wireless power transmitter comprising:

• a power stage circuit;
• a power transmission coil coupled to the power stage circuit;
• a demodulator circuit including:
• a data input node coupled to the power transmission coil;
• a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input coupled to the data input node, the inverting input coupled to the output;
• a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal;
• a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit;
• and
• a data output node coupled to the second terminal of the SH circuit;
• and
• a controller having an input coupled to the data output node, and a controller output coupled to the power stage circuit.

A demodulator circuit comprising:

• a data input node adaptive to be coupled to a wireless power transmission coil;
• a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input coupled to the data input node, the inverting input coupled to the output;
• a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal;
• a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit;
• and
• a data output node coupled to the second terminal of the SH circuit, the data output node configured to output a data signal for regulating power transmission by the wireless power transmission coil.