Semiconductor Heterostructure with P-type Superlattice
AssigneeSensor Electronic Technology, Inc.
InventorMohamed Lachab
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Abstract
A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.
Claims20
A heterostructure comprising:
- an active region including at least one quantum well and at least one barrier;
- an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition;
- and
- an asymmetric p-type superlattice layer located adjacent to the electron blocking layer, wherein the p-type superlattice layer includes at least one superlattice period comprising a plurality of wells and a plurality of barriers, and wherein a thickness of at least one of:
- each well in the plurality of wells or each barrier in the plurality of barriers varies along a length of the p-type superlattice layer.
An optoelectronic device comprising:
- an n-type contact layer;
- an active region including at least one quantum well and at least one barrier located adjacent to the n-type contact layer;
- an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition;
- a p-type superlattice layer located adjacent to the electron blocking layer, wherein the p-type superlattice layer includes at least one superlattice period comprising a plurality of wells and a plurality of barriers, and wherein a thickness of at least one of:
- each well in the plurality of wells or each barrier in the plurality of barriers varies along a length of the p-type superlattice layer;
- and
- a p-type contact layer located adjacent to the p-type superlattice layer, wherein the p-type contact layer has a thickness less than 15 nanometers.
An optoelectronic device comprising:
- a group III nitride n-type contact layer;
- a group III nitride active region including at least one quantum well and at least one barrier, wherein the active region is located adjacent to the n-type contact layer;
- a group III nitride electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition;
- a group III nitride p-type superlattice layer located adjacent to the electron blocking layer, wherein the p-type superlattice layer includes at least one superlattice period comprising a plurality of wells and a plurality of barriers, and wherein a thickness of at least one of:
- each well in the plurality of wells or each barrier in the plurality of barriers varies along a length of the p-type superlattice layer;
- and
- a group III nitride p-type contact located adjacent to the p-type superlattice layer.
Dependencies are inferred from the claim text.