2-D Material Transistor with Vertical Structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJean-Pierre COLINGE, Chung-Cheng WU, Carlos H. DIAZ, Chih-Hao WANG, Ken-Ichi GOTO, Ta-Pen GUO, Yee-Chia YEO, Zhiqiang WU, Yu-Ming LIN
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Abstract
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
Claims20
A method of fabricating a semiconductor structure, comprising:
- providing a substrate with a fin thereon, wherein the fin comprises first and second sidewalls and a top surface;
- depositing a first dielectric layer on the fin, wherein the first dielectric layer covers the first and second sidewalls and the top surface of the fin;
- depositing a two-dimensional (2-D) material layer on the first dielectric layer;
- depositing a second dielectric layer on the 2-D material layer;
- depositing an electrode layer on the second dielectric layer;
- and
- patterning the electrode layer and the second dielectric layer to form a gate stack having a length shorter than that of the 2-D material layer.
A semiconductor structure, comprising:
- a substrate comprising a fin, wherein the fin comprises sidewalls and a top surface;
- an insulating region disposed on the substrate and covering a bottom portion of the sidewalls of the fin;
- a dielectric layer disposed on the top surface of the fin and on the sidewalls of the fin not covered by the insulating region;
- a two-dimensional (2-D) material layer disposed on the dielectric layer, wherein the 2-D material layer extends over the insulating region;
- and
- a gate stack disposed on a portion of the 2-D material layer over the top surface and sidewalls of the fin.
A semiconductor structure, comprising:
- a substrate comprising first and second fins separated by an inner gate region;
- a first two dimensional (2-D) material layer between a first sidewall of the first fin and a first sidewall of the second fin;
- a second 2-D material layer between a second sidewall of the first fin and a second sidewall of the second fin, wherein the inner gate region is between the first and second 2-D material layers;
- a first outer gate region disposed on a portion of the first 2-D material layer opposite from the inner gate region;
- and
- a second outer gate region disposed on a portion of the second 2-D material layer opposite to the inner gate region.
Dependencies are inferred from the claim text.