Dual gate metal-oxide-semiconductor field-effect transistor

A method for fabricating a dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:

• forming a MOSFET having a channel region, a drain, and a source;
• forming a first gate proximate to the channel region;
• forming a drain extension region proximate to the drain;
• and
• forming a second gate proximate to the drain extension region.

An integrated circuit design system for synthesizing an integrated circuit design, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device stores a plurality of instructions that when executed by the processor provides at least one software module that includes:
• a logic synthesizer module that receives a circuit description and a cell technology file to generate functional logic of the integrated circuit design;
• wherein the cell technology file includes a characterization of a dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a MOSFET having a channel region, a drain, and a source and further comprising a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region, that further describes the dual-gate MOSFET as a single MOSFET device which is operable to two different states based on a toggling variable;
• and
• wherein the logic synthesizer module generates the functional logic of the integrated circuit design including the dual-gate MOSFET.

A method for synthesizing an integrated circuit design, comprising:

• storing in a memory device a plurality of instructions;
• executing, by a processor, the plurality of instructions to provide at least one software module that includes a logic synthesizer module;
• receiving, by the logic synthesizer module, a circuit description and a cell technology file;
• generating, by the logic synthesizer module, functional logic of the integrated circuit design;
• characterizing, within the cell technology file, a dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a MOSFET having a channel region, a drain, and a source and further comprising a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region, in which the dual-gate MOSFET is described as a single MOSFET device which is operable to two different states based on a toggling variable;
• and
• generating, by the logic synthesizer module, the functional logic of the integrated circuit including the dual-gate MOSFET.

A computer program product for synthesizing an integrated circuit design, the computer program product comprising a computer usable medium having computer readable code physically embodied therein, said computer program product further comprising computer readable program code for:

• storing in a memory device a plurality of instructions;
• executing, by a processor, the plurality of instructions to provide at least one software module that includes a logic synthesizer module;
• receiving, by the logic synthesizer module, a circuit description and a cell technology file;
• generating, by the logic synthesizer module, functional logic of the integrated circuit design;
• characterizing, within the cell technology file, a dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a MOSFET having a channel region, a drain, and a source and further comprising a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region, in which the dual-gate MOSFET is described as a single MOSFET device which is operable to two different states based on a toggling variable;
• and
• generating, by the logic synthesizer module, the functional logic of the integrated circuit including the dual-gate MOSFET.