Semiconductor apparatus and method of manufacturing the same
AssigneeMitsubishi Electric Corporation
InventorsKenji Suzuki, Mitsuru Kaneda, Koichi Nishi
Life of this patent
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Abstract
A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.
Claims17
A semiconductor apparatus comprising a semiconductor substrate including a cell region in which a semiconductor device is provided, the semiconductor substrate having a front surface and a rear surface,
- the semiconductor device including an n-type drift region, a p-type base region, an n-type emitter region, a gate insulating layer provided on a portion of the p-type base region sandwiched between the n-type emitter region and the n-type drift region, a gate electrode facing the portion of the p-type base region with the gate insulating layer between the gate electrode and the portion, a p-type collector layer provided in the rear surface, a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region,
- the first n-type buffer layer being in contact with the n-type drift region and being provided on a rear surface side with respect to the n-type drift region,
- the second n-type buffer layer being in contact with the first n-type buffer layer and being provided on a rear surface side with respect to the first n-type buffer layer, a first maximum peak concentration of first n-type carriers in the first n-type buffer layer being lower than a second maximum peak concentration of second n-type carriers in the second n-type buffer layer, the first n-type buffer layer being thicker than the second n-type buffer layer,
- the first p-type semiconductor region being formed in the first n-type buffer layer,
- the first p-type semiconductor region having a narrower width than the first n-type buffer layer in a direction in which the n-type emitter region and the gate electrode are arranged,
- the first p-type semiconductor region being spaced away from the p-type collector layer and the p-type base region.
A method of manufacturing a semiconductor apparatus, the method comprising:
- preparing a semiconductor substrate, the semiconductor substrate having a front surface and a rear surface, the semiconductor substrate including, in a cell region of the semiconductor substrate, an n-type drift region, a p-type base region, an n-type emitter region, a gate insulating layer provided on a portion of the p-type base region sandwiched between the n-type emitter region and the n-type drift region, and a gate electrode facing the portion of the p-type base region with the gate insulating layer between the gate electrode and the portion;
- forming a first n-type buffer layer by doping with a first n-type dopant from the rear surface, the first n-type buffer layer being in contact with the n-type drift region and being provided on a rear surface side with respect to the n-type drift region;
- forming a first p-type semiconductor region in the first n-type buffer layer by doping with a first p-type dopant from the rear surface, the first p-type semiconductor region having a narrower width than that of the first n-type buffer layer in a direction in which the n-type emitter region and the gate electrode are arranged;
- forming a second n-type buffer layer by doping with a second n-type dopant from the rear surface, the second n-type buffer layer being in contact with the first n-type buffer layer and being provided on a rear surface side with respect to the first n-type buffer layer, a first maximum peak concentration of first n-type carriers in the first n-type buffer layer being lower than a second maximum peak concentration of second n-type carriers in the second n-type buffer layer, the first n-type buffer layer being thicker than the second n-type buffer layer;
- and
- forming a p-type collector layer in the rear surface by doping with a second p-type dopant from the rear surface;
- the first p-type semiconductor region being spaced away from the p-type collector layer and the p-type base region.
Dependencies are inferred from the claim text.