Contact Plugs and Methods Forming Same

An integrated circuit device comprising:

• a semiconductor region;
• a gate stack over the semiconductor region;
• a first gate spacer contacting a sidewall of the gate stack, wherein the first gate spacer comprises a low-k dielectric material;
• a second gate spacer contacting a sidewall of the first gate spacer, wherein the second gate spacer comprises an L-shape layer, and an additional layer overlapping a bottom leg of the L-shaped layer;
• a contact etch stop layer having a vertical portion contacting the second gate spacer;
• and
• an inter-layer dielectric contacting the contact etch stop layer.

An integrated circuit device comprising:

• a semiconductor fin;
• a gate stack on sidewalls and a top surface of the semiconductor fin;
• a gate spacer on a sidewall of the gate stack;
• a contact etch stop layer having a vertical portion contacting the gate spacer;
• an inter-layer dielectric contacting the contact etch stop layer;
• and
• a high-k dielectric hard mask over and contacting the gate spacer, the contact etch stop layer, and the inter-layer dielectric.