US 2019/0103472 A1 · Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Abstract

A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

Claims21

Dependent claims

A semiconductor device, comprising:

a substrate;
an I/O device over the substrate;
and
a core device over the substrate,
wherein the I/O device includes a first gate structure having:
an interfacial layer;
a first high-k dielectric stack over the interfacial layer;
and
a conductive layer over and in physical contact with the first high-k dielectric stack,
wherein the core device includes a second gate structure having:
the interfacial layer;
a second high-k dielectric stack over the interfacial layer;
and
the conductive layer over and in physical contact with the second high-k dielectric stack, and
wherein the first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

12 more elements

Dependencies are inferred from the claim text.

Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Life of this patent

Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Life of this patent

Abstract

Claims21