Surround gate vertical field effect transistors including tubular and strip electrodes and method of making the same

A method of forming a semiconductor structure, comprising:

• forming a stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer over a substrate, wherein the doped semiconductor strips have a first width along a first horizontal direction and laterally extend along a second horizontal direction, and the one-dimensional array of gate electrode strips have a second width along the second horizontal direction and laterally extend along the first horizontal direction;
• forming a two-dimensional array of openings through the dielectric matrix layer and the one-dimensional array of gate electrode strips;
• forming a two-dimensional array of tubular gate electrode portions in the two-dimensional array of openings, wherein each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips;
• forming gate dielectrics on inner sidewalls of the tubular gate electrode portions;
• and
• forming vertical semiconductor channels within each of the gate dielectrics by deposition of a semiconductor material.

A semiconductor structure, comprising:

• a plurality of vertical semiconductor channel pillars extending in a vertical direction perpendicular to a top surface of a substrate;
• bottom and top active regions contacting respective bottom and top ends of the vertical semiconductor pillars;
• gate dielectrics surrounding respective vertical semiconductor channel pillars;
• gate electrodes surrounding respective gate dielectrics and vertical semiconductor channel pillars;
• and
• gate electrode strips which are thinner than the gate electrodes in the vertical direction, wherein each gate electrode strip contacts one of top or bottom parts of a plurality of the gate electrodes.