Semiconductor apparatus and equipment
AssigneeCanon Kabushiki Kaisha
InventorsHiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
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Abstract
A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
Claims20
A semiconductor apparatus comprising a stack of a first chip and a second chip, wherein the first chip has a plurality of pixel circuits arranged in a matrix form of J rows and K columns, and the second chip has a plurality of electric circuit arranged in a matrix form of T rows and U columns,
- wherein the first chip includes a first semiconductor layer having a plurality of semiconductor elements configuring the plurality of pixel circuits and a first wiring structure including M wiring layers configuring the plurality of pixel circuits;
- wherein the second chip includes a second semiconductor layer having a plurality of semiconductor elements configuring the plurality of electric circuits and a second wiring structure including N wiring layers configuring the plurality of electric circuits,
- wherein the first wiring structure is placed between the first semiconductor layer and the second semiconductor layer,
- wherein the second wiring structure is placed between the first wiring structure and the second semiconductor layer,
- wherein a first conductive portion included in an M-th wiring layer of the first wiring structure from the first semiconductor layer and connected to a circuit of the plurality of pixel circuits and a second conductive portion included in an N-th wiring layer of the second wiring structure from the second semiconductor layer and connected to a circuit of the plurality of electric circuit are electrically connected,
- wherein a third conductive portion included in the M-th wiring layer and connected to a circuit of the plurality of pixel circuits and a fourth conductive portion included in the N-th wiring layer and connected to a circuit of the plurality of electric circuit are electrically connected,
- wherein a shortest wiring path from the second conductive portion to the plurality of semiconductor elements configuring the plurality of pixel circuits is a first length, and a shortest wiring path from the first conductive portion to the plurality of semiconductor elements configuring the plurality of electric circuits is a second length,
- wherein a shortest wiring path from the fourth conductive portion to the plurality of semiconductor elements configuring the plurality of pixel circuits is a third length, and a shortest wiring path from the third conductive portion to the plurality of semiconductor elements configuring the plurality of electric circuit is a fourth length,
- wherein a sum of the third length and the fourth length is longer than a sum of the first length and the second length.
A semiconductor apparatus comprising a stack of a first chip and a second chip, wherein the first chip has a plurality of pixel circuits arranged in a matrix form of J rows and K columns, and the second chip has a plurality of electric circuit arranged in a matrix form of T rows and U columns,
- wherein the first chip includes a first semiconductor layer having a plurality of semiconductor elements configuring the plurality of pixel circuits and a first wiring structure including M wiring layers configuring the plurality of pixel circuits, wherein the second chip includes a second semiconductor layer having a plurality of semiconductor elements configuring the plurality of electric circuits and a second wiring structure including N wiring layers configuring the plurality of electric circuits,
- wherein the first wiring structure is placed between the first semiconductor layer and the second semiconductor layer,
- wherein the second wiring structure is placed between the first wiring structure and the second semiconductor layer,
- wherein a first conductive portion included in an M-th wiring layer of the first wiring structure from the first semiconductor layer and connected to a first circuit of the plurality of pixel circuits and a second conductive portion included in an N-th wiring layer of the second wiring structure from the second semiconductor layer and connected to a second circuit of the plurality of electric circuit are electrically connected,
- wherein a shortest wiring path from the second conductive portion to the plurality of semiconductor elements configuring the plurality of pixel circuits is a first length, and a shortest wiring path from the first conductive portion to the plurality of semiconductor elements configuring the plurality of electric circuits is a second length, and
- wherein the first length is longer than the second length.
A semiconductor apparatus comprising a stack of a first chip and a second chip, wherein the first chip has a plurality of pixel circuits arranged in a matrix form of J rows and K columns, and the second chip has a plurality of electric circuit arranged in a matrix form of T rows and U columns,
- wherein the first chip includes a first semiconductor layer having a plurality of semiconductor elements configuring the plurality of pixel circuits,
- wherein the second chip includes a second semiconductor layer having a plurality of semiconductor elements configuring the plurality of electric circuits,
- wherein the first wiring structure is placed between the first semiconductor layer and the second semiconductor layer,
- wherein the second wiring structure is placed between the first wiring structure and the second semiconductor layer,
- wherein a first semiconductor element configuring a first electric circuit of the plurality of electric circuits is electrically connected to at least one of the plurality of semiconductor elements configuring the plurality of pixel circuits through a first connecting unit configuring the first wiring structure and the second wiring structure,
- wherein a second semiconductor element configuring a second electric circuit of the plurality of electric circuit is electrically connected to at least one of the plurality of semiconductor elements through the first connecting unit configuring the first wiring structure and the second wiring structure, and
- wherein a shortest distance from the second semiconductor element to a semiconductor element connected to the second connecting unit of the plurality of semiconductor elements configuring the plurality of pixel circuits is longer than a shortest distance from the first semiconductor element to a semiconductor element connected to the first connecting unit of the plurality of semiconductor elements configuring the plurality of pixel circuits.
Dependencies are inferred from the claim text.