Embedded sonos with a high-k metal gate and manufacturing methods of the same

A memory device, comprising:

• a substrate disposed within a single semiconductor die;
• a plurality of non-volatile memory (NVM) transistors formed in a first region of the substrate, wherein at least one NVM transistor comprises a blocking dielectric including a second high dielectric constant (high-K) dielectric layer overlying a blocking oxide;
• and
• a plurality of metal-oxide-semiconductor (MOS) transistors formed in a second region of the substrate, wherein the plurality of MOS transistors include a high voltage (HV) MOS transistor, an input/output (I/O) MOS transistor, and a low voltage (LV) MOS transistor, a gate dielectric layer of the HV MOS, I/O MOS, and LV MOS transistors having distinctively different thicknesses from one another, and each including a first high dielectric constant (high-K) dielectric layer overlying a gate oxide including nitrided silicon oxide, and wherein a first gate metal layer is disposed overlying the gate dielectric layers of the HV MOS, I/O MOS, and LV MOS transistors.

A semiconductor system, comprising:

• a system-on-chip (SOC) device;
• a plurality of logic devices;
• and an embedded non-volatile memory (NVM) device disposed within one single semiconductor die, wherein:
• the embedded NVM device includes a plurality of metal-oxide-nitride-oxide-semiconductor (MONOS) transistors, where at least one MONOS transistor includes a first metal gate layer overlying a blocking dielectric including a first high dielectric constant (high-K) dielectric layer disposed overlying a blocking oxide, and
• the SOC device and the plurality of logic devices include high voltage (HV) metal-oxide-semiconductor (MOS) transistors, input/output (I/O) MOS transistors, and low voltage (LV) MOS transistors, wherein gate dielectric of each of the HV MOS, I/O MOS, and LV MOS transistors includes a second high-K dielectric layer, and wherein the gate dielectric of the HV MOS transistors are thicker than the gate dielectric of the I/O MOS transistors, and the gate dielectric of the I/O MOS transistors are thicker than the gate dielectric of the LV MOS transistors, and wherein the gate dielectric of the LV MOS transistors include nitrided silicon oxide.