US 2019/0103407 A1 · SEMICONDUCTOR MEMORY DEVICES

Abstract

Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Claims22

Dependent claims

A semiconductor memory device comprising:

a substrate;
a plurality of memory cell transistors vertically stacked on the substrate;
a first conductive line connected to a source region of at least one of the plurality of memory cell transistors;
a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors;
and
a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors,
wherein the data storage element comprises a first electrode that extends horizontally from the drain region in a first direction parallel to a top surface of the substrate,
wherein a first one of the first conductive line or the second conductive line extends horizontally in a second direction that intersects the first direction, and
wherein a second one of the first conductive line or the second conductive line extends vertically in a third direction that is perpendicular to the top surface of the substrate.

6 more elements

A semiconductor memory device comprising:

a substrate;
a vertical stack comprising a plurality of layers on the substrate;
and
a first conductive line that is penetrated by the vertical stack and that extends in a vertical direction perpendicular to a top surface of the substrate,
wherein each of the plurality of layers of the vertical stack comprises:
a first extended portion that extends horizontally in a first direction parallel to the top surface of the substrate;
and
a second extended portion that extends horizontally from the first extended portion in a second direction parallel to the top surface of the substrate and crossing the first direction,
wherein the first extended portion comprises a second conductive line,
wherein the second extended portion comprises a semiconductor pattern and an electrode that is connected to the semiconductor pattern,
wherein the semiconductor pattern is between the second conductive line and the electrode, and
wherein the first conductive line is on a top surface and a bottom surface of the semiconductor pattern.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor memory devices

Life of this patent

Semiconductor memory devices

Life of this patent

Abstract

Claims22