Esd protection circuit and method of making the same

A method comprising:

• providing a substrate having a device region with an electrostatic discharge (ESD) protection circuit;
• forming a gate over the device region;
• forming a source region in the device region having a n-type (N+) implant and a p-type (P+) implant laterally separated on a first side of the gate;
• and
• forming a drain region in the device region on a second side of the gate, opposite the first.

A device comprising:

• a substrate including a device region with an electrostatic discharge (ESD) protection circuit;
• a gate over the device region;
• a source region having an embedded n-type (N+) implant on opposite sides of the source region and a p-type (P+) implant in the device region under a grounded pad on a first side of the gate, wherein the P+ implant is separated from each N+ region by 80 nm to 100 nm;
• a N+ drain region in the device region on a second side of the gate, opposite the first;
• another N+ implant, wherein an edge of each N+ implant is aligned with an opposite edge of the source region and the P+ implant is laterally separated therebetween;
• and
• a low-voltage p-well (LVPW) formed in the device region prior to a formation of each of the N+ and P+ implants and wherein the N+ and P+ implants and a portion of the another N+ implant are in the LVPW.