Integrated circuit device having esd protection
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Lin Peng, Li-Wei Chu, Yi-Feng Chang, Jam-Wem Lee
Life of this patent
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Abstract
An integrated circuit device with ESD protection includes a substrate with a well having a first conductivity type formed on the substrate. A drain region has at least one drain diffusion with a second conductivity type implanted in the well and at least one drain conductive insertion on the well. The drain conductive insertion is electrically connected to the drain diffusion and an I/O pad. A source region includes a plurality of source diffusions having the second conductivity type implanted in the well, and the source diffusions are electrically connected to a voltage terminal.
Claims20
An integrated circuit device with ESD protection, comprising:
- a substrate;
- a well having a first conductivity type formed on the substrate;
- a drain region comprising at least one drain diffusion having a second conductivity type implanted in the well and at least one drain conductive insertion on the well, the drain conductive insertion being electrically connected to the drain diffusion and an I/O pad;
- and
- a source region comprising a plurality of source diffusions having the second conductivity type implanted in the well, the source diffusions being electrically connected to a voltage terminal.
A method of providing ESD protection to an integrated circuit device, comprising:
- providing a substrate;
- forming a well having a first conductivity type on the substrate;
- implanting at least one drain diffusion having a second conductivity type in the well;
- depositing at least one drain conductive insertion on the well;
- electrically connecting the at least one drain diffusion and the at least one drain polysilicon insertion to an I/O pad;
- implanting a plurality of source diffusions having the second conductivity type in the well;
- and
- electrically connecting the source diffusions to a voltage terminal;
- wherein a parasitic transistor includes an emitter formed by the plurality of source diffusions, a base formed by the well, and a collector formed by the at least one drain diffusion, and wherein the parasitic transistor provides an ESD current path between the voltage terminal and the I/O pad.
An integrated circuit device with ESD protection, comprising:
- a substrate;
- a well having a first conductivity type formed on the substrate;
- and
- a parasitic transistor having an emitter formed by a plurality of source diffusions having a second conductivity type implanted in the well, a base formed by the well, and a collector formed by at least one drain diffusion having the second conductivity type implanted in the well.
Dependencies are inferred from the claim text.