Pin modification for standard cells

A computer system comprising:

• a memory configured to store instructions;
• and
• a processor, that when executing the instructions, is configured to perform operations for routing a standard cell with a plurality of pins, the operations comprising:
• modifying a dimension of at least one pin from the plurality of pins, wherein the at least one pin is spaced at an increased distance from a boundary of the standard cell than an original position of the at least one pin;
• routing an interconnect from the at least one pin to a via placed on a pin track located between the at least one pin and the boundary;
• inserting a wire cut between the interconnect and at least one pin from an adjacent standard cell;
• and
• verifying the wire cut separates the interconnect from the at least one pin of the adjacent standard cell by at least a predetermined distance.

A non-transitory computer-readable medium having instructions stored thereon that, when executed by a computing device, causes the computing device to perform operations comprising:

• modifying a dimension of at least one pin from the plurality of pins, wherein the at least one pin is spaced at an increased distance from a boundary of the standard cell than an original position of the at least one pin;
• routing an interconnect from the at least one pin to a via placed on a pin track located between the at least one pin and the boundary;
• inserting a wire cut between the interconnect and at least one pin from an adjacent standard cell;
• and
• verifying the wire cut separates the interconnect from the at least one pin of the adjacent standard cell by at least a predetermined distance.