Metallic Interconnect, a Method of Manufacturing a Metallic Interconnect, a Semiconductor Arrangement and a Method of Manufacturing a Semiconductor Arrangement

A method of manufacturing a semiconductor arrangement, the method comprising:

• forming a first metallic layer on the semiconductor device, the first metallic layer comprising first microstructures protruding from the first metallic layer, the first metallic layer and the first microstructures being at least partially covered by a first metal-oxide and one or more organic materials;
• providing a substrate comprising a second metallic layer having second microstructures protruding from the second metallic layer, the second metallic layer and the second protruding structures being at least partially covered by a second metal-oxide and the one or more organic materials;
• contacting the first microstructures and the second microstructures to form a mechanical connection between the semiconductor device and the substrate, the mechanical connection being configured to allow fluid to penetrate the mechanical connection;
• removing the first metal-oxide and the second metal-oxide with a reducing agent that penetrates the mechanical connection and reacts with the first metal-oxide and the second metal-oxide;
• and
• heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form a metallic interconnection between the semiconductor device and the substrate as well as removal of the one or more organic materials.

A semiconductor device arrangement, comprising:

• a substrate;
• and
• a semiconductor device mechanically and electrically connected to the substrate via a metallic interconnection comprising a porous region and one or more adjacent regions contiguous with the porous region,
• wherein the metallic interconnection comprises a pure metal,
• wherein the porous region of the pure metal has a higher porosity than the one or more adjacent regions of the metallic interconnection.

A semiconductor arrangement, comprising:

• a substrate;
• a composite layer comprising a porous polymer material having voids throughout with metallic structures penetrating through the porous polymer material on the substrate;
• and
• a semiconductor device on the composite layer;
• wherein the metallic structures form an electrically conductive connection between the substrate and the semiconductor device,
• wherein the porous polymer material is configured to decouple stress between the substrate and the semiconductor device.