Standard Cell Layout for Better Routability

A multi-layer semiconductor device structure in an integrated circuit (IC) comprising:

• a plurality of cells arranged on a substrate and fabricated using a fabrication technology having a metal-0 oxide diffusion (M0OD) layer and a polysilicon (PO) layer;
• a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths wherein at least one metal-1 conduction path in the first set of conduction paths extends across multiple cells;
• and
• a metal-2 layer having a first set of metal-2 conduction paths and a second set of metal-2 conduction paths;
• wherein the first set of metal-1 conduction paths and the first set of metal-2 conduction paths are configured to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.

A method for fabricating an integrated circuit comprising:

• fabricating a plurality of cells on a substrate, the plurality of cells comprising a metal-0 oxide diffusion layer and a polysilicon (PO) layer;
• fabricating a first portion of a metal-1 layer over the plurality of cells using a mask A;
• after fabricating the first portion of the metal-1 layer, fabricating a second portion of the metal-1 layer over the plurality of cells using a mask B;
• and
• after fabricating the second portion of the metal-1 layer, fabricating a metal-2 layer over the plurality of cells.