Integrated circuit substrate and method of making
AssigneeIntel Corporation
InventorsRahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
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Abstract
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
Claims20
A substrate for an integrated circuit, the substrate comprising:
- a dielectric layer;
- and
- a conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer, the conductive layer comprising:
- a via having a first end and an opposite second end, wherein the via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end, and the via has a substantially non-tapered profile in the z-direction;
- and
- a trace adjacent to the via and having a second height in the z-direction that is different than the first height.
A substrate for an integrated circuit, the substrate comprising:
- a dielectric layer;
- and
- a metallic transmission line, comprising:
- a first region having a first width in an x or y direction and a first height in a z-direction;
- and
- a second region having a second width in the x or y direction and a second height in the z-direction,
- wherein the first height is greater than the second height and the first region has a constant cross-sectional shape in the z-direction.
A method for forming a substrate, the method comprising:
- contacting a first patterned region with an electrolytic copper composition comprising:
- a copper salt;
- and
- a rate controlling agent;
- contacting a second patterned region with the electrolytic copper composition comprising:
- a copper salt;
- and
- a rate controlling agent;
- wherein a first quantity of the rate controlling agent in the first region differs from second quantity of the rate controlling agent in the second region and the first and second regions are defined by plurality of dry film resist elements, wherein a first distance in an x or y direction in the first region between a first pair of adjacent dry film resist elements is greater than a second distance in the x or y direction in the second region between a second pair of adjacent dry film resist elements;
- applying a voltage to the electrolytic copper composition to plate a copper layer in the patterned regions;
- removing the dry film resist elements;
- and
- laminating a second dielectric layer on the copper layer.
Dependencies are inferred from the claim text.