Wafer scale testing and initialization of small die chips

A chip intermediate body manufacturing system for manufacturing a chip intermediate body, the chip intermediate body comprising:

• a semiconductor region cut from a wafer, with the semiconductor region including a plurality of chip areas, the chip areas respectively being cut out as semiconductor chips;
• a cut region provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips;
• a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas;
• and
• an insulating layer with embedded electric wiring provided continuously with the cut region to connect the chip areas and the contact region.

A semiconductor chip manufacturing system, comprising:

• a fabrication unit for fabricating a chip intermediate body including a semiconductor region cut from a wafer, a cut region, a contact region, and electric wiring, the semiconductor region including a plurality of chip areas respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the chip areas across the cut region, the electric wiring being embedded in an insulating layer and provided continuously with the cut region to connect the chip areas and the contact region;
• a test unit for testing the chip areas, the test unit including a probe to contact the contact region to test the chip areas;
• and
• a separation unit for cutting the cut region to cut out the semiconductor chips.