Method of forming vertical field effect transistors with different gate lengths and a resulting structure

A method comprising:

• forming a sacrificial layer on a semiconductor substrate such that the sacrificial layer has a first portion and a second portion, wherein a height of a top surface of the first portion of the sacrificial layer as measured from a planar bottom surface of the semiconductor substrate is less than a height of a top surface of the second portion of the sacrificial layer as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first portion of the sacrificial layer is below a level of the top surface of the second portion of the sacrificial layer;
• forming a semiconductor layer on the sacrificial layer;
• planarizing the semiconductor layer;
• patterning the semiconductor layer into a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being above the first portion of the sacrificial layer and the second semiconductor fin being above the second portion of the sacrificial layer such that the first semiconductor fin is taller than the second semiconductor fin;
• etching the sacrificial layer to expose the semiconductor substrate;
• forming a first lower source/drain region on the semiconductor substrate adjacent to the first semiconductor fin and a second lower source/drain region on the semiconductor substrate adjacent to the second semiconductor fin such that a top surface of the first lower source/drain region is below a level of a top surface of the second lower source/drain region;
• and
• forming a first transistor with the first lower source/drain region and the first semiconductor fin and a second transistor with the second lower source/drain region and the second semiconductor fin.

A structure comprising:

• a semiconductor substrate;
• a first transistor comprising a first lower source/drain region on the semiconductor substrate and a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region;
• and
• a second transistor comprising a second lower source/drain region on the semiconductor substrate and a second semiconductor fin extending upward from a top surface of the second lower source/drain region,
• wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and
• wherein the first semiconductor fin and the second semiconductor fin comprise monocrystalline epitaxial semiconductor material and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively.