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US 2019/0103313 A1Published application
Carrier substrate, package, and method of manufacture
AssigneeUbotic Company Limited
InventorMing-Wa TAM
Life of this patent
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Abstract
A method of manufacturing, a carrier, and a semiconductor package are provided. The method involves depositing a plurality of conductive vias, applying a molding material over the lead frame, grinding the molding material to expose the plurality of conductive vias, and depositing a metalized pattern over the molding material. The carrier is manufacture by this method and the semiconductor package is formed based on the carrier.
Claims20
A method of manufacturing a carrier, the method comprising:
- depositing a plurality of conductive vias on a top surface of a lead frame;
- applying a molding material over the lead frame, wherein the molding material covers the top surface of the lead frame and the plurality of conductive vias, and wherein the molding material exposes a bottom surface of the lead frame;
- grinding the molding material to expose the plurality of conductive vias;
- and
- depositing a metalized pattern over the molding material, wherein the metalized pattern is in electrical communication with the plurality of conductive vias.
2 more elements
A substrate for receiving a chip, the substrate comprising:
- a lead frame having a top surface and a bottom surface;
- a plurality of conductive vias deposited on the top surface of the lead frame;
- a molding material applied over the lead frame, wherein the molding material covers the top surface of the lead frame and exposes the plurality of conductive vias;
- and
- a metalized pattern deposited on the molding material, wherein the metalized pattern is in electrical communication with the plurality of conductive vias.
2 more elements
A semiconductor package comprising:
- a lead frame having a top surface and a bottom surface, wherein the lead frame comprises dual rows of leads and a die attach pad;
- a plurality of conductive vias deposited on the top surface of the lead frame;
- a molding material applied over the lead frame, wherein the molding material covers the top surface of the lead frame and exposes the plurality of conductive vias;
- a metalized pattern deposited on the molding material, wherein the metalized pattern is in electrical communication with the plurality of conductive vias;
- and
- a flip chip attached to the metalized pattern, wherein connectors of the flip chip are in communication with the dual rows of leads and the die attach pad.
3 more elements
Dependencies are inferred from the claim text.