FinFET Device and Method of Manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsiang-Wei Lin
Life of this patent
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Abstract
A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
Claims20
A method comprising:
- forming a semiconductor fin protruding from a substrate;
- forming a gate stack over the semiconductor fin;
- forming a first dielectric material on sidewalls of the gate stack;
- forming source and drain regions adjacent the gate stack;
- forming a second dielectric material on the top and sidewalls of the source and drain regions and on the first dielectric material;
- performing an etching process to form openings in the second dielectric material, the openings exposing the source and drain regions;
- and
- forming a third dielectric material on the second dielectric material, the third dielectric material different from the second dielectric material.
A method comprising:
- patterning a substrate to form a semiconductor strip;
- forming a dummy gate stack over a channel region of the semiconductor strip;
- forming gate spacers on sidewalls of the dummy gate stack;
- epitaxially growing a source/drain region adjacent the channel region;
- forming a conformal capping layer over the gate spacers and the source/drain region;
- performing an etching process on the capping layer, the etching process forming an opening in the capping layer over the source/drain region;
- and
- after performing the etching process, forming an Inter-Layer Dielectric (ILD) over the capping layer.
A semiconductor device comprising:
- a fin extending from an upper surface of a substrate;
- a gate stack disposed over the fin;
- a first dielectric material disposed on a sidewall of the gate stack;
- an epitaxy region disposed adjacent gate stack;
- a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a first thickness of a first portion over the epitaxy region that is smaller than a second thickness of a second portion over the epitaxy region, wherein the second portion is disposed closer to the substrate than the first portion;
- a third dielectric material disposed on the second dielectric material;
- and
- a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
Dependencies are inferred from the claim text.