Method for manufacturing semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
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Abstract
A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
Claims20
A method for manufacturing a semiconductor device, the method comprising:
- forming a structure protruding from a substrate;
- forming a dielectric layer covering the structure;
- forming a dummy layer covering the dielectric layer;
- and
- performing a planarization process to completely remove the dummy layer,
- wherein a material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
A method for manufacturing a memory device, the method comprising:
- forming first transistors on a first region of a substrate and second transistors on a second region of the substrate;
- forming an array of memory cells in the first region and electrically connected to the first transistors;
- forming a dielectric layer covering the memory cells and extending to the second region of the substrate;
- forming a dummy layer covering the entire upper surface of the dielectric layer;
- and
- performing a planarization process directly to the dummy layer,
- wherein a material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
A method for manufacturing a memory device, the method comprising:
- forming first transistors on a first region of a substrate and second transistors on a second region of the substrate;
- forming interlayer dielectric layers and contacts in the interlayer dielectric layers to electrically connected to the first transistors and the second transistors;
- forming an array of memory cells in the first region and electrically connected to the first transistors;
- forming a dielectric layer covering the memory cells and extending to the second region of the substrate;
- forming a dummy layer made of one selected from the group consisting of TiN, TaN, USG oxide, SiON, TEOS, and a combination thereof to cover the entire upper surface of the dielectric layer;
- and
- performing a planarization process directly to the dummy layer until the dummy layer is completely removed.
Dependencies are inferred from the claim text.