Techniques to reduce substrate reflow warpage
AssigneeIntel Corporation
InventorsChristopher David Combs, Steven Vandervoort
Life of this patent
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Abstract
Apparatus and methods are provided to reduce warpage of an integrated circuit package while reflowing solder to couple a first substrate of a first electronic device with a second substrate or second electronic device. In an example, the method can include placing an anti-warpage fixture onto the first electronic device to provide a captured electronic device, placing the captured electronic device and the anti-warpage fixture on the second substrate, and reflowing the captured electronic device to the second substrate. In certain examples, the method can include limiting a clearance distance between the first substrate and the second substrate to a minimum distance.
Claims21
An apparatus for limiting warpage of an integrated circuit package during solder reflow, the apparatus comprising:
- a first portion configured to rest on a first electronic device of the integrated circuit package opposite a bottom surface of the first electronic device, the first electronic device comprising a first substrate, and an integrated circuit electrically coupled to the first substrate, wherein a bottom surface of the first substrate includes a connector for electrically coupling to a second substrate during the solder reflow, and wherein the bottom surface of the first substrate forms the bottom surface of the first electronic device;
- a pair of clips extending from the first portion, each clip having a vertical portion extending directly from the first portion and a clip end extending from the vertical portion distal from the first portion, wherein a lower surface of the first portion, the vertical portion of each clip, and the corresponding clip end are configured to partially enclose a portion of the integrated circuit package when the first portion is at rest on the first electronic device;
- and
- wherein each clip is configured to provide a minimum stand-off distance between the first substrate and the second substrate during the solder reflow.
A method of reducing warpage of an integrated circuit package while reflowing solder to couple a first substrate of a first electronic device with a second substrate, the method comprising:
- placing an anti-warpage fixture onto the first electronic device to provide a captured electronic device;
- placing the captured electronic device and the anti-warpage fixture on the second substrate;
- reflowing the captured electronic device to the second substrate;
- and
- wherein the reflowing includes limiting a minimum offset distance between the first substrate and the second substrate.
Dependencies are inferred from the claim text.