Back to results
US 2019/0103284 A1Published application
Silicon Reflow for Reducing Seam and Void and Bending During Gap Fill
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDe-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
Life of this patent
Estimating the term…
Abstract
A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
Claims20
A method comprising:
- depositing a first silicon layer, wherein the first silicon layer comprises first portions over a plurality of strips that protrudes higher than a base structure, and second portions filled into trenches between the plurality of strips;
- performing a first anneal to allow parts of the first portions of the first silicon layer to migrate toward lower parts of the trenches;
- and
- performing a first etching on the first silicon layer to remove some portions of the first silicon layer.
1 more element
A method comprising:
- forming source/drain regions on a plurality of semiconductor fins, wherein the plurality of semiconductor fins is between a plurality of dummy gate stacks;
- forming a dielectric layer on the source/drain regions and the plurality of dummy gate stacks;
- fully filling trenches between the plurality of dummy gate stacks with a semiconductor material, wherein the fully filling the trenches comprises:
- performing a first deposition-anneal-etching cycle to form a first semiconductor layer over the dielectric layer, with the first semiconductor layer partially filling trenches between the plurality of dummy gate stacks;
- planarizing the semiconductor material, until the plurality of dummy gate stacks is exposed;
- replacing the plurality of dummy gate stacks with replacement gates;
- and
- removing remaining portions of the semiconductor material and the first semiconductor layer.
5 more elements
A method comprising:
- performing a plurality of deposition-anneal-etch cycles to stack a plurality of semiconductor layers, with the plurality of semiconductor layers comprising first portions over a plurality of dummy gate stacks, and second portions partially filling trenches between the plurality of dummy gate stacks, and the plurality of dummy gate stacks protrude over isolation regions, wherein each of the plurality of deposition-anneal-etch cycles comprises:
- depositing a conformal semiconductor layer;
- performing an anneal on the conformal semiconductor layer to turn the conformal semiconductor layer into a non-conformal layer having a bottom-thick profile;
- and
- performing an etching to partially remove the non-conformal layer;
- and
- filling remaining portions of the trenches with an additional semiconductor layer.
4 more elements
Dependencies are inferred from the claim text.