Memory system and method of operating the same

A memory system comprising:

• a semiconductor memory device including a plurality of memory cells to be programmed to an erase state and a plurality of program state;
• and
• a controller configured to control the semiconductor memory device to perform a first program operation, a second program operation, a program-fail-bit-detection operation, or a read operation in response to a request of a host,
• wherein the controller controls the semiconductor memory device such that when, after the first program operation has been performed, a number of program fail bits detected by performing the program-fail-bit-detection operation is greater than a maximum allowed number of error correcting code (ECC) bits, a second program operation is performed on memory cells having a certain program state of the plurality of program states.

A method of operating a memory system, comprising:

• programming program data to a plurality of memory cells;
• performing a program-fall-bit-detection operation on the plurality of memory cells;
• and
• selectively performing, when a number of program fail bits detected as a result of the program-fail-bit-detection operation is greater than a maximum allowed number of error correcting code (ECC) bits, a re-program operation on memory cells having a certain program state of the plurality of memory cells.