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US 2019/0103168 A1Published application
Error reducing matrix generation
AssigneeWestern Digital Technologies, Inc.
InventorsMAI GHALY, CHANDAN MISHRA, AMIR HOSSEIN GHOLAMIPOUR, YUHENG ZHANG, JEFFREY KOON YEE LEE, JAMES HART, DANIEL HELMICK
Life of this patent
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Abstract
Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.
Claims20
An apparatus comprising:
- a test circuit that performs a test on a set of memory cells;
- a masking circuit that determines a masking array based on the test performed on the set of memory cells;
- and
- a decoding circuit that decodes encoded data from the set of memory cells based on the masking array.
1 more element
A system comprising:
- a controller;
- and
- an array of storage locations, wherein the controller, in response to a failure to decode undecoded data stored on the array of storage locations, is configured to:
- write test data to each storage location of the array of storage locations;
- read the test data stored on each storage location of the array of storage locations;
- compare the test data written to each storage location with the test data read from each storage location;
- and
- form an error location matrix based on the comparison between the test data written to each storage location and the test data read from each storage location.
5 more elements
An apparatus comprising:
- means for testing operation of a memory block in response to a failure to decode data of the memory block during a decoding operation;
- means for determining portions of the memory block that caused the failure to decode the data of the memory block during the decoding operation;
- and
- means for decoding the data of the memory block by masking the determined portions of the memory block that caused the failure.
1 more element
Dependencies are inferred from the claim text.