Shift register unit, method for driving shift register unit, gate driving circuit and display device

A shift register unit, comprising a first transistor, a second transistor, a first capacitor, a third transistor, a second capacitor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an input end, a first output end and a second output end;

• a control electrode of the first transistor is coupled to a first pull-up node, a first electrode of the first transistor is coupled to a timing control signal end, and a second electrode of the first transistor is coupled to a second pull-up node;
• a control electrode of the second transistor is coupled to the first pull-up node, a first electrode of the second transistor is coupled to a first clock signal end, and a second electrode of the second transistor is coupled to the first output end;
• the first capacitor is coupled to the control electrode and the second electrode of the second transistor;
• a control electrode of the third transistor is coupled to the second pull-up node, a first electrode of the third transistor is coupled to a second clock signal end, and a second electrode of the third transistor is coupled to the second output end;
• the second capacitor is coupled to the control electrode and the second electrode of the third transistor;
• a control electrode of the fourth transistor is coupled to the input end, a first electrode of the fourth transistor is coupled to a first voltage end, and a second electrode of the fourth transistor is coupled to the first pull-up node;
• a control electrode and a first electrode of the fifth transistor are coupled to the first voltage end, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor;
• a control electrode of the sixth transistor is coupled to the input end, the first electrode of the sixth transistor is further coupled to a control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to a second voltage end;
• the control electrode of the seventh transistor is further coupled to the second electrode of the fifth transistor, a first electrode of the seventh transistor is coupled to a pull-down control signal end, and a second electrode of the seventh transistor is coupled to a first electrode of the eighth transistor;
• a control electrode of the eighth transistor is coupled to the input end, the first electrode of the eighth transistor is further coupled to a pull-down node, and a second electrode of the eighth transistor is coupled to the second voltage end;
• a control electrode of the ninth transistor is coupled to the pull-down node, a first electrode of the ninth transistor is coupled to the first pull-up node, and a second electrode of the ninth transistor is coupled to the second voltage end;
• and
• a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the second pull-up node, and a second electrode of the tenth transistor is coupled to the second voltage end.

A shift register unit, comprising a first transistor, a second transistor, a first capacitor, a third transistor, a second capacitor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, an input end, a first output end and a second output end;

• a control electrode of the first transistor is coupled to a first pull-up node, a first electrode of the first transistor is coupled to a timing control signal end, and a second electrode of the first transistor is coupled to a second pull-up node;
• a control electrode of the second transistor is coupled to the first pull-up node, a first electrode of the second transistor is coupled to a first clock signal end, and a second electrode of the second transistor is coupled to the first output end;
• the first capacitor is coupled to the control electrode and the second electrode of the second transistor;
• a control electrode of the third transistor is coupled to the second pull-up node, a first electrode of the third transistor is coupled to a second clock signal end, and a second electrode of the third transistor is coupled to the second output end;
• the second capacitor is coupled to the control electrode and the second electrode of the third transistor;
• a control electrode and a first electrode of the fifth transistor are coupled to a first voltage end, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor;
• a control electrode of the sixth transistor is coupled to the input end, the first electrode of the sixth transistor is further coupled to a control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to a second voltage end;
• the control electrode of the seventh transistor is further coupled to the second electrode of the fifth transistor, a first electrode of the fifth transistor is coupled to a pull-down control signal end, and a second electrode of the fifth transistor is coupled to a first electrode of the eighth transistor;
• a control electrode of the eighth transistor is coupled to the input end, the first electrode of the eighth transistor is further coupled to a pull-down node, and a second electrode of the eighth transistor is coupled to the second voltage end;
• a control electrode of the ninth transistor is coupled to the pull-down node, a first electrode of the ninth transistor is coupled to the first pull-up node, and a second electrode of the ninth transistor is coupled to the second voltage end;
• a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the second pull-up node, and a second electrode of the tenth transistor is coupled to the second voltage end;
• a control electrode and a first electrode of the thirteenth transistor are coupled to the input end, and a second electrode of the thirteenth transistor is coupled to a first electrode of the fourteenth transistor;
• a control electrode of the fourteenth transistor is coupled to the input end, a first electrode of the fourteenth transistor is coupled to a control electrode of the fifteenth transistor, and a second electrode of the fourteenth transistor is coupled to the first pull-up node;
• the control electrode and a second electrode of the fifteenth transistor are coupled to the second electrode of the thirteenth transistor, and a first electrode of the fifteenth transistor is coupled to the first voltage end;
• a control electrode of the sixteenth transistor is coupled to the control electrode of the fifteenth transistor, a first electrode of the sixteenth transistor is coupled to the first voltage end, and a second electrode of the sixteenth transistor is coupled to the first pull-up node;
• a control electrode of the seventeenth transistor is coupled to the pull-down node, a first electrode of the seventeenth transistor is coupled to the first pull-up node, and a second electrode of the seventeenth transistor is coupled to the second electrode of the fifteenth transistor;
• and
• a control electrode of the eighteenth transistor is coupled to the pull-down node, a first electrode of the eighteenth transistor is coupled to the second electrode of the seventeenth transistor, and a second electrode of the eighteenth transistor is coupled to the second voltage end.