Back to results
US 2019/0103161 A1Published application
Access signal adjustment circuits and methods for memory cells in a cross-point array
AssigneeUnity Semiconductor Corporation
InventorsChristophe Chevallier, Chang Hua Siau
Life of this patent
Estimating the term…
Abstract
Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
Claims21
(canceled)
A memory device comprising:
- a first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices;
- and
- a target magnitude generator coupled to the first two-terminal cross-point array, the target magnitude generator comprising a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
An apparatus comprising:
- a substrate;
- a first two-terminal cross-point array formed above the substrate, the first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices;
- and
- a target magnitude generator formed on the substrate and coupled to the first two-terminal cross-point array, the target magnitude generator comprising a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
1 more element
An integrated circuit comprising:
- a logic layer formed on a substrate, the logic layer comprising a target magnitude generator;
- and
- a memory comprising one or more layers formed above the substrate, the memory comprising a first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices,
- wherein the target magnitude generator comprises a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
1 more element
Dependencies are inferred from the claim text.