Memory circuit having shared word line
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro FUJIWARA, Li-Wen WANG, Yen-Huei CHEN, Hung-Jen LIAO
Life of this patent
Estimating the term…
Abstract
A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
Claims20
A circuit comprising:
- a column of memory cells;
- a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells;
- a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells;
- and
- a plurality of read word lines,
- wherein each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
A memory circuit comprising:
- a column of memory cells, wherein a first subset of memory cells of the column of memory cells alternates with a second subset of memory cells of the column of memory cells;
- a plurality of read word lines, wherein each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with an adjacent memory cell of the second subset of memory cells;
- a read amplifier;
- and
- a multiplexer unit configured to selectively couple either the first subset of memory cells or the second subset of memory cells to the read amplifier.
A memory circuit comprising:
- a column of memory cells, wherein a first subset of memory cells of the column of memory cells alternates with a second subset of memory cells of the column of memory cells;
- a plurality of read word lines, wherein each read word line of the plurality of read word lines is coupled with first and second pass gates of a memory cell of the first subset of memory cells and with first and second pass gates of an adjacent memory cell of the second subset of memory cells;
- a first read data line coupled with the first pass gates of the first and second subsets of memory cells;
- and
- a second read data line coupled with the second pass gates of the first and second subsets of memory cells.
Dependencies are inferred from the claim text.