Full-rail digital read compute-in-memory circuit
AssigneeIntel Corporation
InventorsHuseyin Ekin SUMBUL, Gregory K. CHEN, Raghavan KUMAR, Phil Ekin KNAG, Abhishek SHARMA, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Ram A. KRISHNAMURTHY, Ian A. YOUNG
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Abstract
A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.
Claims23
An integrated circuit comprising:
- a memory array of memory cells to store weights in row major order, a weight having multiple bit positions, each bit position mapped to a corresponding column of the memory array, a stored bit of the weight stored in a memory cell in the corresponding column;
- a memory access circuit to initiate a read operation on a single memory array row;
- and
- a sampling capacitance network connected to the memory access circuit, the sampling capacitance network to weight the read operation according to the mapped bit positions, the weighted read operation to capture a value of the weight stored in the single memory array row.
An apparatus, comprising:
- a compute-in-memory (CIM) circuit, the CIM circuit comprising a computation circuit coupled to a memory array, the computation circuit comprising:
- a memory access circuit to initiate a read operation on a single memory array row of the memory array;
- and
- a sampling capacitance network connected to the memory access circuit, the sampling capacitance network to weight the read operation according to a mapped bit position of a weight stored in the single memory array row.
A system comprising:
- a processor;
- a memory device communicatively coupled with the processor, the memory device including a compute-in-memory (CIM) circuit, the CIM circuit comprising a computation circuit coupled to a memory array, the computation circuit comprising:
- a memory access circuit to initiate a read operation on a single memory array row of the memory array;
- and
- a sampling capacitance network connected to the memory access circuit, the sampling capacitance network to weight the read operation according to mapped bit positions of a weight stored in the single memory array row, the mapped bit positions corresponding to memory array columns spanning the single memory array row.
Dependencies are inferred from the claim text.