US 2019/0103150 A1 · MINIMIZING TWO-STEP AND HARD STATE TRANSITIONS IN MULTI-LEVEL STT_MRAM DEVICES

Abstract

Data is stored in a multi-level MRAM (MLC MRAM) cell in a manner that reduces transition states that require high energy. A new data block is received, and the new data block is divided into one or more sub-groups of bits, with each sub-group comprising at least two bits. Each sub-group is assigned data bit locations in a memory store. The received bits are compared with sub-groups present at the data bit locations to determine subgroups of hot bits. For each subgroup of hot bits, an encoding flag value is determined by XORing their most significant bits. The most significant bits of each subgroup of hot bits are complemented and the encoding flag is SET. A data block is generated to establish a data group for each subgroup of hot bits including the subgroup of hot bits and the encoding flag for that subgroup.

Claims9

Dependent claims

A method for minimizing two-step and hard transitions in a multi-level STT-MRAM device, comprising the steps of:

receiving a new data block;
dividing the new data block into one or more sub groups of bits, each sub group comprising at least two bits;
assigning each sub group data bit locations in a memory store;
comparing the sub groups of bits in the received new data block with sub groups present at the data bit locations in the memory store to determine subgroups of hot bits;
for each subgroup of hot bits, determining an encoding flag value by XORing their most significant bits;
complementing the most significant bits of each subgroup of hot bits and SET the encoding flag, and generating a data block so as to establish a data group for each subgroup of hot bits comprised of the subgroup of hot bits and the encoding flag for that subgroup;
and
storing the data group at the data bit locations.

5 more elements

A multi-level MRAM (MLC RAM) cell, comprising:

means for receiving a new data block;
means for dividing the new data block into one or more sub groups of bits, each sub group comprising at least two bits and assigning each sub group data bit locations in a memory store;
means for comparing the sub groups of bits in the received new data block with sub groups present at the data bit locations in the memory store to determine subgroups of hot bits;
means for, for each subgroup of hot bits, determining an encoding flag value by XORing their most significant bits, and complementing the most significant bits of each subgroup of hot bits and SET the encoding flag;
means for generating a data group for each subgroup of hot bits comprised of the subgroup of hot bits and the encoding flag for that subgroup;
and
means for storing the data group at the data bit locations.

4 more elements

Dependencies are inferred from the claim text.

Minimizing two-step and hard state transitions in multi-level stt_mram devices

Life of this patent

Minimizing two-step and hard state transitions in multi-level stt_mram devices

Life of this patent

Abstract

Claims9