Apparatuses and methods for targeted refreshing of memory
AssigneeMicron Technology, Inc.
InventorsWilliam F. Jones, Jeffrey P. Wright
Life of this patent
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Abstract
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
Claims20
A method, comprising:
- determining whether a target row of memory is a row of primary memory or a row of redundant memory;
- in response to a determination that the target row of memory is a row of primary memory, refreshing a first primary memory row and a second primary memory row of the primary memory, wherein the first primary memory row and the second primary memory row are each physically adjacent the accessed row of memory;
- and
- in response to a determination that the target row of memory is a row of redundant memory, refreshing a first redundant memory row and a second redundant memory row of the redundant memory, wherein the first redundant memory row and the second redundant memory row are each physically adjacent the accessed row of memory.
An apparatus comprising:
- a row redundancy control circuit configured to receive a row address associated with a target row of memory and to provide a control signal if the target row of memory is a row of redundant memory;
- a row address predecoder circuit configured to receive the row address and the control signal, and to provide a first row address and a second row address, wherein when the control signal is not being provided the first address and the second address are associated with a respective a first primary memory row and a second primary memory row each physically adjacent to the target row of memory, and wherein when the control signal is being provided the first address and the second address are associated with a respective first redundant memory row and a second redundant memory row of the redundant memory which are physically adjacent to the target row of memory.
Dependencies are inferred from the claim text.