State dependent sense circuits and pre-charge operations for storage devices

A circuit comprising:

• a communications bus;
• a sense circuit coupled to a bit line, the sense circuit comprising:
• a pre-charge circuit path configured to:
• increase a sense voltage at a sense node to a pre-charge level;
• a latch circuit configured to:
• float relative to the communications bus to allow the pre-charge circuit path to increase the sense voltage to the pre-charge level in response to the bit line comprising a selected bit line;
• and
• pull down a voltage of the communications bus to an associated low voltage level to prevent the pre-charge circuit path from increasing the sense voltage to the pre-charge level.

A system comprising:

• a memory block comprising memory cells and a plurality of bit lines connected to the memory cells;
• a first sense circuit connected to a first bit line of the plurality of bit lines during a sense operation, the first sense circuit comprising a first transistor configured to supply a pre-charge supply voltage to a first sense node;
• a first latch circuit configured to turn on the first transistor in response to the first bit line comprising a selected bit line in order to allow the first transistor to supply the pre-charge supply voltage;
• a second sense circuit connected to a second bit line of the plurality of bit lines during the sense operation, the second sense circuit comprising a second transistor configured to supply the pre-charge supply voltage to a second sense node;
• and
• a second latch circuit configured to turn off the second transistor in response to the second bit line comprising an unselected bit line in order to prevent the second transistor from supplying the pre-charge supply voltage.