Memory device and method of operating same

A semiconductor device comprising:

• a sense amplifier including first and second terminals;
• first and second terminal switches connected correspondingly between the first and second terminals of the sense amplifier and corresponding first and second nodes;
• first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes;
• and
• first and second capacitors connected correspondingly between the third and fourth nodes and a first reference voltage;
• and
• wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows:
• during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered correspondingly into the first and second capacitors from corresponding selected ones of bit lines arranged in an array, the bit lines being connected correspondingly to the first and second nodes and to corresponding memory cells;
• and
• during a reuse phase in which the first and second gleaned charges are reused from the first and second capacitors correspondingly through the first and second nodes onto selected corresponding ones of the array of bit lines.